List of Publications

Refereed International Journals/Books

  1. C. Metra, B. Riccò, "Enhanced reliability evaluation for self-checking circuits", in IEE Electronics Letters, Vol. 30, No. 10, pp.776–778, 12 May, 1994, Institution of Electrical Engineers, Stevenage SG1 2AY (United Kingdom), 1994.
  2. C. Metra, M. Favalli, B. Riccò, "Novel 1-out-of-n CMOS checker", in IEE Electronics Letters, Vol. 30, No. 17, pp. 1398–1400, 18 August, 1994, Institution of Electrical Engineers, Stevenage SG1 2AY (United Kingdom), 1994.
  3. C. Metra, M. Favalli, B. Riccò, "Design of CMOS self-checking sequential circuits with improved detectability of bridging faults", in IEE Electronics Letters, Vol. 30, No. 23, pp. 1934–1936, 10 November, 1994, Institution of Electrical Engineers, Stevenage SG1 2AY (United Kingdom), 1994.
  4. C. Metra, "Circuiti CMOS Self-Checking" (Tesi di Dottorato), Bologna, Febbraio 1994.
  5. C. Metra, M. Favalli, P. Olivo, B. Riccò, "Design of CMOS Checkers with Improved Testability of Bridging and Transistor Stuck-on Faults", in Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 6, No. 1, pp. 7–22, February 1995, Kluwer Academic Publishers, Norwell, MA 02061 (USA), 1995.
  6. C. Metra, M. Favalli, B. Riccò, "Design of TSC CMOS Checkers for Any 1-out-of-n Code", in Journal of Microelectronic Systems Integration, Vol. 3, No. 2, pp. 109–120, 1995, Plenum Publishing Corporation, New York (USA), 1995.
  7. C. Metra, M. Favalli, "1-out-of-n dynamic CMOS checker", in IEE Electronics Letters, Vol. 31, No. 23, 9 November, pp. 1999-2000, 1995, Institution of Electrical Engineers, Stevenage SG1 2AY (United Kingdom), 1995.
  8. M. Favalli, C. Metra, "Sensing circuit for on-line detection of delay faults", in IEEE Transactions on VLSI Systems, Vol. 4, No. 1, pp. 130-133, March 1996, The Institute of Electrical and Electronics Engineers Inc., Piscataway, (NJ), 1996.
  9. M. Favalli, C. Metra, "Design of low-power CMOS two-rail checkers", in Journal of Microelectronic Systems Integration, Vol. 5, No. 2, pp. 101–110, 1997, Plenum Publishing Corporation, New York (USA), 1997.
  10. C. Metra, M. Favalli, B. Riccò, "1-out-of-3 Code Checker with Single Output", in IEE Electronics Letters, Vol. 33, No. 16, 31 July, pp. 1373-1374, 1997, Institution of Electrical Engineers, Stevenage SG1 2AY (United Kingdom), 1997.
  11. C. Metra, M. Favalli, P. Olivo, B. Riccò, "On-Line Detection of Bridging and Delay Faults in Functional Blocks of CMOS Self-Checking Circuits", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD/ICAS), Vol. 16, No. 7, July, pp. 770-776, 1997, The Institute of Electrical and Electronics Engineers Inc., Piscataway, (NJ), 1997.
  12. C. Metra, M. Favalli, B. Riccò, "On-Line Self-Testing Voting and Detecting Schemes for TMR Systems", in Journal of Microelectronic Systems Integration, Vol. 5, No. 4, pp. 261–273, 1997, Plenum Publishing Corporation, New York (USA), 1997.
  13. C. Metra, "Design Technique for Embedded 1-out-of-3 Checkers", in Alta Frequenza Rivista di Elettronica, Vol. 9, No 2, pp. 68-70, 1997, Associazione Elettrotecnica ed Elettronica Italiana, Milano, 1997.
  14. C. Metra, M. Favalli, B. Riccò, ”Concurrent Checking of Clock Signals’ Correctness”, in IEEE Design & Test of Computers, Vol. October - November, pp. 42–48, 1998, IEEE Computer Society Press, Los Alamitos (California), 1998.
  15. (Invited Paper) C. Metra, "Majority Logic", in Wiley Encyclopedia of Electrical and Electronics Engineering, Vol. 12, pp. 317--322, February 1999, Wiley & Sons., Inc., Publishers, New York (USA), 1999.
  16. (Invited conference report) C. Metra, Neil Harrison, "DFT Symposium 98", in IEEE Design & Test of Computers, Vol. January-March, p. 5, 1999, IEEE Computer Society Press, Los Alamitos (California), e in The Newsletter of the Test Technology Technical Council of the IEEE Computer Society, Amissville, VA 937-7848 (USA), 1999.
  17. M. Favalli, C. Metra, "Bus Crosstalk Fault Detection Capabilities of Error Detecting Codes for On-Line Testing", in IEEE Transactions on VLSI Systems, Vol. 7, No. 3, pp. 392–396, Settembre, 1999, The Institute of Electrical and Electronics Engineers Inc., Piscataway, (NJ), 1999.
  18. (Invited conference report) C. Metra, Neil Harrison, "Defect and Fault Tolerance Symposium 1999", in Test Technology Newsletter - The Newsletter of the Test Technology Technical Council of the IEEE Computer Society, October-December, 1999, TTTC Office, 1474 Freeman Drive, Amissville, VA 20106 (USA), 1999.
  19. C. Metra, M. Favalli, B. Riccò, "Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits", in VLSI Design, Vol. 11, No. 1, 2000, pp. 23–34, OPA N.V., published by licence under the Gordon and Breach Science (ISSN: 1065-514X), Newark, NJ 07102, printed in Malaysia, 2000.
  20. C. Metra, M. Favalli, B. Riccò, "Self-Checking Detection and Diagnosis Scheme for Transient, Delay and Crosstalk Faults Affecting Bus Lines", in IEEE Transactions on Computers, Vol. 49, No. 6, June 2000, pp. 560–574, IEEE Computer Society Press, Los Alamitos (California), 2000
  21. M. Favalli, C. Metra, "Bridging Faults in Pipelined Circuits", in Journal of Electronic Testing: Theory and Applications, Vol. 16, Issue 6, December 2000, pp. 617—629, Kluwer Academic Publishers, Norwell, MA 02061 (USA), 2000.
  22. C. Metra, J-C. Lo, "Intermediacy Prediction for High Speed Berger Code Checkers", in Journal of Electronic Testing: Theory and Applications, Vol. 16, Issue 6, December 2000, pp. 607–615, Kluwer Academic Publishers, Norwell, MA 02061 (USA), 2000.
  23. Lombardi, C. Metra, "Defect-Oriented Diagnosis for Very Deep-Submicron Systems", in IEEE Design & Test of Computers, Vol. January-February, pp. 8–9, 2001, IEEE Computer Society Press, Los Alamitos (California), 2001.
  24. C. Metra, B. Riccò, "Soluzioni Hardware per Sistemi Integrati Digitali ad Alta Sicurezza", in Alta Frequenza Rivista di Elettronica, Vol. 13, No 3, pp. 4-10, Maggio-Giugno 2001, Associazione Elettrotecnica ed Elettronica Italiana, Milano, 2001.
  25. Favalli, C. Metra, "On-Line Testing Approach for Very Deep-Submicron ICs", in IEEE Design & Test of Computers, Vol. March-April, 2002, pp. 16—23, IEEE Computer Society Press, Los Alamitos (California), 2002.
  26. D. Nikolos, J. Hayes, M. Nicolaidis, C. Metra, "Guest Editorial of the Special Issue on the 7th IEEE International On-Line Testing Workshop", in The Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 18, n. 3, pp. 259--260, June 2002, Kluwer Academic Publishers, Norwell, MA 02061 (USA), 2002.
  27. M. Favalli, C. Metra, "Single output distributed two-rail checker with diagnosing capabilities for bus based self-checking architectures", in Journal of Electronic Testing: Theory and Applications, Vol. 18, n. 3, pp. 273-283, June 2002, Kluwer Academic Publishers, Norwell, MA 02061 (USA), 2002.
  28. C. Metra, M. Favalli, S. Di Francescantonio, B. Riccò, "On-Chip Clock Faults' Detector", in The Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 18, n. 4, pp. 555-564, August, 2002, Kluwer Academic Publishers, Norwell, MA 02061 (USA), 2002.
  29. C. Metra, S. Di Francescantonio, M. Favalli, B. Riccò, "Scan Flip-Flops with On-Line Testing Ability with respect to input Delay and Crosstalk Faults", in Microelectronics Journal, Vol. 34, n. 1, pp. 23-29, January, 2003, Elsevier Science (ISSN 0026-2692).
  30. C. Metra, M. Sonza Reorda, "Guest Editorial”, in The Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 19, No. 5, October 2003, p. 499, Kluwer Academic Publishers, Norwell, MA 02061 (USA), 2003.
  31. D. Rossi, C. Metra, "Error correcting strategy for high speed and density reliable flash memories", in The Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 19, No. 5, October 2003, pp. 511-521, Kluwer Academic Publishers, Norwell, MA 02061 (USA), 2003.
  32. L. Schiano, C. Metra, D. Marino, "Self-Checking Design, Implementation and Measurement of a Controller for Track-Side Railway Systems", in IEEE Transactions on Instrumentation and Measurement, Vol. 52, No. 6, pp. 1722—1728, December 2003, The Institute of Electrical and Electronics Engineers Inc., Piscataway, (NJ), 2003.
  33. C. Metra, L. Schiano, M. Favalli, "Concurrent Detection of Power Supply Noise", in IEEE Transactions on Reliability, Vol. 52, No. 4, pp. 469—475, December 2003, The Institute of Electrical and Electronics Engineers Inc., Piscataway, (NJ), 2003.
  34. A. Ivanov, F. Lombardi, C. Metra, "Guest Editors’ Introduction: Advances in VLSI Testing at MultiGbps Rates”, in IEEE Design & Test of Computers, Vol. July-August, 2004, pp. 274—276, IEEE Computer Society Press, Los Alamitos (California), 2004.
  35. C. Metra, S. Di Francescantonio, TM Mak, "Implications of Clock Distribution Faults and Issues with Screening Them During Manufacturing Testing", in IEEE Transactions on Computers, Vol. 53, No. 5, May 2004, IEEE Computer Society Press, Los Alamitos (California), 2004.
  36. M. Omaña, D. Rossi, C. Metra, "Model for Transient Fault Susceptibility of Combinational Circuits", in The Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 20, No. 5, pp. 495—503, October 2004, Kluwer Academic Publishers, Norwell, MA 02061 (USA), 2004.
  37. M. Favalli, C. Metra, "TMR Voting in the Presence of Crosstalk Faults at the Voter Inputs", in IEEE Transactions on Reliability, Vol. 53, No. 3, pp. 342—348, September 2004, The Institute of Electrical and Electronics Engineers Inc., Piscataway, (NJ), 2004.
  38. J. M. Cazeaux, D. Rossi and C. Metra, “Self-Checking Voter for High Speed TMR Systems", in The Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 21, No. 4, August 2005, pp. 377—389, Springer, Springer Boston/Norwell (USA), 2005, ISSN: 0923-8174.
  39. D. Rossi, A. K. Neiuwland, A. Kotoch and C. Metra, “Exploiting ECC Redundancy To Minimize Crosstalk Impact”, in IEEE Design & Test of Computers, Vol. 22, N. 1, January-February, 2005, pp. 59—70, IEEE Computer Society Press, Los Alamitos (California), 2005.
  40. D. Rossi, A. K. Nieuwland, A. Katoch, C. Metra, “New ECC for Crosstalk Impact Minimization”, in IEEE Design & Test of Computers, July-August, 2005, pp.340—348, IEEE Computer Society Press, Los Alamitos (California), 2005.
  41. M. Omaña, D. Rossi, C. Metra, "Low Cost and High Speed Embedded Two-Rail Code Checker", in IEEE Transactions on Computers, Vol. 54, Issue 2, February 2005, pp. 153—164, IEEE Computer Society Press, Los Alamitos (California), 2005.
  42. J. M. Cazeaux, M. Omaña, and C. Metra, “Novel On-Chip Circuit for Jitter Testing in High-speed PLLs”, in IEEE Transactions on Instrumentations and Measurements, Vol. 54, Issue 5, October 2005, pp. 1779—1788, The Institute of Electrical and Electronics Engineers Inc., Piscataway, (NJ), 2005.
  43. C. Metra, D. Rossi, TM. Mak, “Won’t On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?”, in IEEE Transactions on Computers, Vol. 56, No. 3, March, 2007, pp. 415-428, IEEE Computer Society Press, Los Alamitos (California), 2007.
  44. D. Rossi, J. M. Cazeaux, C. Metra, F. Lombardi, "Modeling Crosstalk Effects in CNT Bus Architectures", in IEEE Transactions on Nanotechnology, Vol. 6, No. 2, March, 2007, pp. 133-145, The Institute of Electrical and Electronics Engineers Inc., Piscataway, (NJ), 2000
  45. D. Rossi, A.K. Nieuwland, C. Metra, "Simultaneous Switching Noise: The Relation Between Bus Layout and Coding", in IEEE Design & Test of Computers, Vol. 25, Issue 1, January-February 2008, pp.76-86, IEEE Computer Society Press, Los Alamitos (California), 2008.
  46. M. Omaña, D. Rossi, C. Metra, “Latch Susceptibility to Transient Faults and New Hardening Approach”, in IEEE Transactions on Computers, Vol. 56, Issue 9, September 2007, pp. 1255-1268, IEEE Computer Society Press, Los Alamitos (California), 2007.
  47. Lombardi, C. Metra, "Guest Editors’ Introduction: The State of the Art in Nanoscale CAD", in IEEE Design & Test of Computers, Vol. 24, July-August, pp. 302--303, 2007, IEEE Computer Society Press, Los Alamitos (California), 2007.
  48. (Book Chapter) X. Ma, J. Huang, C. Metra, F. Lombardi, "Reversible and Testable Circuits for Molecular QCA Design", in “Emerging Nanotechnologies”, ISSN 0929-1296, ISBN 978-0-387-74746-0, pp. 157-202, Springer US, 2007.
  49. D. Rossi, M. Omaña, C. Metra, "Checker No-Harm Alarms and Design Approaches to Tolerate Them", in The Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 24, Issue 1-3, June 2008, pp. 93-103, Springer, Springer Boston/Norwell (USA), 2008, ISSN: 0923-8174.
  50. (Updated Invited Paper) C. Metra, "Majority Logic", in Wiley Encyclopedia of Electrical and Electronics Engineering, pp. 1-8, April 2007, Wiley & Sons., Inc., Publishers, New York (USA), 2007, accessible online: eeee@wiley.com.
  51. D. Rossi, A.K. Nieuwland, V.E.S. van Dijk, R.P. Kleihorst, C. Metra, "Power Consumption of Fault-Tolerant Busses", in IEEE Transactions on VLSI Systems, Vol. 16, Issue 5, May 2008, pp. 542-553, The Institute of Electrical and Electronics Engineers Inc., Piscataway, (NJ), 2008.
  52. X. Ma, J. Huang, C. Metra, F. Lombardi, "Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA", The Journal of Electronic Testing: Theory and Applications (JETTA)”, Vol. 24, No. 1-3, pp. 297 – 311, June 2008, Springer, Springer Boston/Norwell (USA), 2008, ISSN: 0923-8174.
  53. D. Rossi, J. M. Cazeaux, M. Omana, C. Metra, A. Chatterjee, "Accurate Linear Model for SET Critical Charge Estimation", IEEE Transactions on VLSI Systems, Vol. 17, No. 8, pp. 1161 – 1166, August 2009, The Institute of Electrical and Electronics Engineers Inc., Piscataway, (NJ), 2009.
  54. M. Favalli, C. Metra, " Testing resistive open and bridging faults through pulse propagation", IEEE Transactions on CAD, Vol. 28, Issue 6, June 2009, pp. 915 – 925, The Institute of Electrical and Electronics Engineers Inc., Piscataway, (NJ).
  55. M. Omaña, D. Rossi, C. Metra, “Latch High Performance Robust Latches”, IEEE Transactions on Computers, Vol. 59, No. 11, pp. 1455 – 1465, November 2010, IEEE Computer Society Press, Los Alamitos (California), 2010.
  56. C. Metra, M. Omaña, TM Mak, S. Tam, “Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors”, IEEE Transactions on VLSI Systems, Vol. 19, No. 12, pp. 2322 – 2325, December 2011, The Institute of Electrical and Electronics Engineers Inc., Piscataway, (NJ), 2011 (TVLSI-00007-2010)
  57. C. Metra, M. Omaña, TM Mak, S. Tam, “New Design For Testability Approach for Clock Fault Testing”, IEEE Transactions on Computers, Vol. 16, No. 61, April 2012, IEEE Computer Society Press, Los Alamitos (California), 2012 (TC-2009-11-0558)
  58. M. Omaña, D. Rossi, N. Bosio, C. Metra, “Low Cost NBTI Degradation Detection & Masking Approaches”, IEEE Transactions on Computers, Vol. 62, No. 3, pp. 496-509, March 2013, IEEE Computer Society Press, Los Alamitos (California), 2013
  59. M. Omaña, D. Rossi, D. Giaffreda, R. Specchia, C. Metra, M. Marzencki, B. Kaminska, “Faults Affecting Energy Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection”, in IEEE Transactions on VLSI Systems, Vol. 21, Issue 12, December 2013, pp. 2286 – 2294, IEEE Computer Society Press, Los Alamitos (California), 2012
  60. D. Rossi, M. Omaña, G. Garrammone, C. Metra, A. Jas, R, Galivanche, “Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder”, The Journal of Electronic Testing: Theory and Applications (JETTA)”, Vol. 29, No. 3, pp. 401 – 413, June 2013, Springer, Springer Boston/Norwell (USA), 2013
  61. R. Vimalathithan, D. Rossi, M. Omaña, C. Metra, M.L.Valarmathi, “Polynomial Based Key Distribution Scheme for WPAN”, Malaysian Journal of Mathematical Sciences, Special Edition of International Conference on Cryptology on Computer Security, Vol. 7(S), pp. 59-72, August 2013, ISSN: 1823-8343
  62. D. Rossi, M. Omaña, J. M. Cazeaux, C. Metra, TM. Mak, “Clock Faults Induced Min and Max Delay Violations”, in Journal of Electronic Testing: Theory and Applications, Volume 30, Issue 1, 2014, pp. 111-123, Springer, Springer Boston/Norwell (USA), 2014, Springer, Springer Boston/Norwell (USA), 2014
  63. M. Omaña, D. Rossi, D. Giaffreda, C. Metra, TM Mak, A. Rahman, S. Tam, “Low-Cost On-Chip Clock Jitter Measurement Scheme”, in IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, Vol. 23, Issue 3, March 2015, pp. 435 – 443, IEEE Computer Society Press, Los Alamitos (California), 2015.
  64. D. Rossi, M. Omaña, C. Metra, A. Paccagnella, “Impact of Bias Temperature Instability on Soft Error Susceptibility”, in IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 23 , Issue 4, April 2015, pp. 743 – 751, IEEE Computer Society Press, Los Alamitos (California), 2015.
  65. D. Rossi, M. Omaña, D. Giaffreda, C. Metra, “Modeling and Detection of Hot-Spot in Shaded Photovoltaic Cells”, IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 23, Issue 6, Giugno 2015, pp. 1031-1039, 2015
  66. R. Vimalathithan, D. Rossi, M. Omana, C. Metra, M. L. Valarmathi, "Cryptanalysis of Simplified-AES Encrypted Communication", International Journal of Computer Science and Security (IJCSIS), Vol. 13 No. 10, Ottobre 2015
  67. M. Omaña, D. Rossi, E. Beniamino, C. Metra, C. Tirumurti, R. Galivanche, “Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST”, IEEE Trans. on Computers, Issue 99, October 2015
  68. M. Omaña, D. Rossi, T. Edara, C. Metra, “Impact of Aging Phenomena on Latches’ Robustness”, IEEE Trans. on Nanotechnology, Issue 2, pp. 129-136, March 2016
  69. M. Omaña, M. Padovani, K. Veliu, C. Metra, J. Alt, R. Galivanche, “New Approaches for Power Binning of High Performance Microprocessors”, to appear on IEEE Trans. on Computers, 2017

Patents

  1. Co-inventor of “A Digital, Parallel, Clock Synchronizer” (provisional US Patent OTT Ref #2505-3193).
  2. Co-inventor (together with Kleihorst Richard, Nieuwland Andre, Van Dijk Victor, Philips Research, Eindhoven, The Netherlands) of “Data Communication Using Fault Tolerant Error Correcting Codes and Having Reduced Ground Bounce” (International Publication Number WO 2005/088465 A1, International Publication Date 22 September 2005).

Refereed International Conferences/Symposia/Workshops

  1. C. Metra, M. Favalli, P. Olivo, B. Riccò, “CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults”, in IEEE Proceedings of International Test Conference, Baltimore (MD, USA), pp. 948–957, September 20-24, 1992, International Test Conference, 2000 L Street, NW, Washington D.C. 20036, 1992.
  2. C. Metra, M. Favalli, P. Olivo, B. Riccò, “Testing of Resistive Bridging Faults in CMOS Flip-Flop”, in IEEE Proceedings of European Test Conference, Rotterdam (The Netherlands), pp. 530–531, April 19-22, 1993, IEEE Computer Society Press, Los Alamitos (California), 1993.
  3. C. Metra, M. Favalli, P. Olivo, B. Riccò, “Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block”, in IEEE Proceedings of The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, Venezia (Italy), pp. 271–278, October 27-29 Ottobre, 1993, IEEE Computer Society Press, Los Alamitos (California), 1993.
  4. C. Metra, M. Favalli, P. Olivo, B. Riccò, “A Highly Testable 1-out-of-3 CMOS Checker”, in IEEE Proceedings of The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, Venezia (Italy), pp. 279–286, October 27-29, 1993, IEEE Computer Society Press, Los Alamitos (California), 1993.
  5. C. Metra, M. Favalli, B. Riccò, “CMOS Self Checking Circuits with Faulty Sequential Functional Blocks”, in IEEE Proceedings of The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, Montreal (Canada), pp. 133–141, October 17-19, 1994, IEEE Computer Society Press, Los Alamitos (California), 1994.
  6. C. Metra, M. Favalli, B. Riccò, “Highly Testable and Compact 1-out-of-n CMOS Checkers”, in IEEE Proceedings of The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, Montreal (Canada), pp.142–150, October 17-19, 1994, IEEE Computer Society Press, Los Alamitos (California), 1994.
  7. C. Metra, “MINIMAL POWER-DELAY PRODUCT CMOS BUFFER”, in Proceedings of Power And Timing Modeling, Optimization and Simulation’94 (PATMOS’94), Barcellona (Spain), pp. 150–157, October 17-19, 1994, UPC, Barcellona (Spain), 1994.
  8. C. Metra, M. Favalli, B. Riccò, “Highly Testable 1-out-of-n Dynamic CMOS Checker”, in Proceedings of 1st IEEE International On-Line Testing Workshop, Nice (France), pp.248–252, July 4-6, 1995, CNRS, Grenoble (Francia), 1995.
  9. C. Metra, M. Favalli, B. Riccò, “Glitch Power Dissipation Model”, in Proceedings of Power And Timing Modeling, Optimization and Simulation’95 (PATMOS’95), Oldenburg (Germany), pp. 175–189, October 4-6, 1995, bis, Oldenburg (Germania), 1995.
  10. M. Favalli, C. Metra, “The effect of glitches on CMOS Buffer Optimization”, in Proceedings of Power And Timing Modeling, Optimization and Simulation’95 (PATMOS’95), Oldenburg (Germany), pp. 202–212, October 4-6, 1995, bis, Oldenburg (Germania), 1995.
  11. C. Metra, M. Favalli, B. Riccò, “Novel Berger Code Checker”, in IEEE CS Proceedings of The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems 1995, Lafayette (Louisiana), pp.287–295, November 13-15, 1995, IEEE Computer Society Press, Los Alamitos (California), 1995.
  12. C. Metra, M. Favalli, B. Riccò, “Embedded Two-Rail Checkers with On-Line Testing Ability”, in IEEE Proceedings of 14th IEEE VLSI Test Symposium, Princeton (New Jersey), pp.145–150, April 28 – May 1, 1996, IEEE Computer Society Press, Los Alamitos (California), 1996.
  13. C. Metra, M. Favalli, B. Riccò, “Embedded 1-out-of-3 Checkers with On-Line Testing Ability”, in Proceedings of 2nd IEEE International On-Line Testing Workshop, Saint-Jean de-Luz, Biarritz (France), pp. 136–141, July 8-10, 1996, CNRS, Grenoble (France), 1996.
  14. C. Metra, Jien-Chung Lo, “Compact and High Speed Berger Code Checker”, in Proceedings of 2nd IEEE International On-Line Testing Workshop, Saint-Jean de-Luz, Biarritz (France), pp. 144–149, July 8-10, 1996, CNRS, Grenoble (Francia), 1996.
  15. C. Metra, M. Favalli, B. Riccò, “Tree Checkers for Applications with Low Power-Delay Requirements”, in IEEE Proceedings of The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston (MA), pp. 213–220, November 6-8, 1996, IEEE Computer Society Press, Los Alamitos (California), 1996.
  16. C. Metra, M. Favalli, B. Riccò, “Compact and Highly Testable Error Indicator for Self-Checking Circuits”, in IEEE Proceedings of The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston (MA), pp. 204–212, November 6-8, 1996, IEEE Computer Society Press, Los Alamitos (California), 1996.
  17. M. Favalli, C. Metra, “Testing scheme for IC’s clock”, in IEEE Proceedings of The European Design & Test Conference and Exhibition 1997, Paris (France), pp. 445–449, March 17-20, 1997.
  18. C. Metra, M. Favalli, B. Riccò, Highly Testable and Compact Single Output Comparator”, in IEEE Proceedings of 15th IEEE VLSI Test Symposium, Monterey (California), pp. 210–215, April 27 – 30, 1997, IEEE Computer Society Press, Los Alamitos (California), 1997.
  19. C. Metra, M. Favalli, B. Riccò, “Novel Single Output –out-of-3 Code Checker”, in Proceedings of 3rd IEEE International On-Line Testing Workshop, Crete (Greece), pp. 228–232, July 7-9, 1997, Dept. of Computer Eng. & Informatics, Univ. of Patras, Greece, 1997.
  20. C. Metra, M. Favalli, B. Riccò, “Self-Checking Detector for Simultaneous On-Line Test of Clock Signals”, in Proceedings of 3rd EEE International On-Line Testing Workshop, Crete (Greece), pp. 79–83, July 7-9, 1997, Dept. of Computer Eng. & Informatics, Univ. of Patras, Greece, 1997.
  21. M. Favalli, C. Metra, “Leakage power reduction for reactive computation”, in Proceedings of Power And Timing Modeling, Optimization and Simulation’97 (PATMOS’97), Louvain-la-Neuve (Belgium), pp. 57–66, September 8-10, 1997, Presses Universitaires de Louvain-la-Neuve, Luovain (Belgium), 1997.
  22. C. Metra, M. Favalli, B. Riccò, “On-Line Testing Scheme for Clocks’ Faults”, in IEEE Proceedings of International Test Conference, Washington, D.C. (USA), pp. 587–596, November 1-6, 1997, International Test Conference, 2000 L Street, NW, Washington D.C. 20036, 1997.
  23. C. Metra, M. Favalli, B. Riccò, “Compact and Low Power Self-Checking Voting Scheme”, in IEEE Proceedings of The International Symposium on Defect and Fault-Tolerance in VLSI Systems, Paris (France), pp. 137–145, October 20-22, 1997, IEEE Computer Society Press, Los Alamitos (California), 1997.
  24. M. Favalli, C. Metra, “Low-level Error Recovery Mechanism for Self-Checking Sequential Circuits”, in IEEE Proceedings of The International Symposium on Defect and Fault-Tolerance in VLSI Systems, Paris (France), pp. 234–242, October 20-22, 1997, EEE Computer Society Press, Los Alamitos (California), 1997.
  25. Y-Y. Guo, J-C. Lo, Cecilia Metra, “Fast and Area-Time Efficient Berger Code Checkers”, in IEEE Proceedings of The International Symposium on Defect and Fault-Tolerance in VLSI Systems, Paris (France), pp.110–118, October 20-22, 1997, IEEE Computer Society Press, Los Alamitos (California), 1997.
  26. C. Metra, M. Favalli, B. Riccò, “Highly Testable and Compact 1-out-of-n Code Checker with Single Output”, in IEEE Proceedings of Design, Automation and Test in Europe, Paris (France), pp. 981–982, February 23-26, 1998, IEEE Computer Society Press, Los Alamitos (California), 1998.
  27. C. Metra, Giovanni Mojoli, Sandro Pastore, Davide Salvi, Giacomo Sechi, “Novel Technique for Testing FPGAs”, in IEEE Proceedings of Design, Automation and Test in Europe, Paris (France), pp. 89–94, February 23-26, 1998, IEEE Computer Society Press, Los Alamitos (California), 1998.
  28. (Invited) C. Metra, “Concurrent Testing Techniques for Clock’s Faults”, in Lecture Notes of the Intel Research Symposium VLSI Test, Santa Clara (CA), pp. 1–47, April 24, 1998, Intel Corporation, Santa Clara (CA).
  29. C. Metra, M. Favalli, B. Riccò, “Novel Implementation for Highly Testable Parity Code Checkers”, in Compendium of Papers of 4th IEEE International On-Line Testing Workshop, Capri (Italy), pp. 167–171, July 6-8, 1998, Politecnico di Torino, Dip. Di Automatica e Informatica, Torino (Italy), 1998.
  30. C. Metra, J-C. Lo, “General Design Method for VLSI High Speed Berger Code Checkers”, in Compendium of Papers of 4th IEEE International On-Line Testing Workshop, Capri (Italy), pp.177–181, July 6-8, 1998, Politecnico di Torino, Dip. Di Automatica e Informatica, Torino (Italy), 1998.
  31. C. Metra, M. Favalli, B. Riccò, “On-Line Detection of Logic Errors due to Crosstalk, Delay and Transient Faults”, in IEEE Proceedings of International Test Conference, Washington, D. C. (USA), pp. 524–533, October 18-23, 1998, International Test Conference, 2000 L Street, NW, Washington D.C. 20036, 1998.
  32. C. Metra, M. Favalli, B. Riccò, “Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks”, in IEEE Proceedings of The IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, Austin (Texas), pp. 174–182, November 2-4, 1998, IEEE Computer Society Press, Los Alamitos (California), 1998.
  33. S. D’Angelo, C. Metra, S. Pastore, A. Pogutz, G. Sechi, “Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-based Systems”, in IEEE Proceedings of The IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, Austin (Texas), pp. 233–240, November 2-4, 1998, IEEE Computer Society Press, Los Alamitos (California), 1998.
  34. M. Favalli, C. Metra, “On the design of self-checking functional units based on Shannon circuits”, in IEEE Proceedings of Design Automation and Test in Europe Conference, Monaco (Germany), pp. 368–375, March 9-12, 1999, IEEE Computer Society Press, Los Alamitos (California), 1999.
  35. C. Metra, F. Giovanelli, M. Soma, B. Riccò, “Self-Checking Scheme for Very Fast Clock’s Skew Correction”, in IEEE Proceedings of International Test Conference, Atlantic City, NJ (USA), pp.~652–661, September 28-30, 1999, International Test Conference, 2000 L Street, NW, Washington D.C. 20036, 1999.
  36. C. Metra, R. Degiampietro, M. Favalli, B. Riccò, “Concurrent Detection and Diagnosis Scheme for Transient, Delay and Crosstalk Faults”, in IEEE Proceedings of 5th IEEE International On-Line Testing Workshop, Rhodes, Greece, pp. 66–70, July 5-7, 1999, Dept. of Computer Eng. & Informatics, Univ. of Patras, Greece, 1999.
  37. C. Metra, S. D’Angelo, G. Sechi, “Low Performance Degradation Transient Fault Recovery for TMR Systems”, in IEEE Proceedings of 5th IEEE International On-Line Testing Workshop, Rhodes, Greece, pp. 44–48, July 5-7, 1999, Dept. of Computer Eng. & Informatics, Univ. of Patras, Greece, 1999.
  38. S. D’Angelo, C. Metra, G. Sechi, “Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems”, in IEEE Proceedings of The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 1-3, 1999, Albuquerque (New Mexico), IEEE Computer Society Press, Los Alamitos (California), 1999.
  39. C. Metra, M. Favalli, B. Riccò, “On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values”, in IEEE Proceedings of Design, Automation and Test in Europe (DATE) Conference, Paris (France), pp.763, March 27-30, 2000, IEEE Computer Society Press, Los Alamitos (California), 2000.
  40. C. Metra, M. Favalli, B. Riccò, “On-Line Testing and Diagnosis Scheme for Intermediate Voltage Values Affecting Bus Lines”, in IEEE Proceedings of IEEE International Defect Based Testing Workshop, Montreal (Canada), pp. 76–81, April 29, 2000, IEEE Computer Society Press, Los Alamitos (California), 2000.
  41. M. Alderighi, S. D’Angelo, C. Metra, G. Sechi, “Achieving Fault Tolerance by Shifted and Rotated Operands in TMR non-Diverse ALUs”, in IEEE Proceedings of The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Mt. Fuji (Japan), pp. 155–163, October 25-27, 2000, IEEE Computer Society Press, Los Alamitos (California), 2000.
  42. M. Favalli, C. Metra, “Optimization of error detecting codes for the detection of crosstalk originated errors”, in IEEE Proceedings of Design, Automation and Test in Europe (DATE) Conference, Munich (Germany), pp. 290–296, March 13-16, 2001, IEEE Computer Society Press, Los Alamitos (California), 2001.
  43. M. Alderighi, S. D’Angelo, C. Metra, G. Sechi, “Novel Fault-Tolerant Adder Design for FPGA – Based Systems”, in IEEE Proceedings of 7th IEEE International On-Line Testing Workshop, Giardini Naxos-Taormina (Italy), pp. 54–58, July 9-11, 2001, IEEE Computer Society Press, Los Alamitos (California), 2001.
  44. M. Favalli, C. Metra, “Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures”, in IEEE Proceedings of 7th IEEE International On-Line Testing Workshop, Giardini Naxos-Taormina (Italy), pp. 100–105, July 9-11, 2001, IEEE Computer Society Press, Los Alamitos (California), 2001.
  45. C. Metra, A. Pagano, B. Riccò, “On-Line Testing of Transient and Crosstalk Faults Affecting Interconnections of FPGA-Implemented Systems”, in IEEE Proceedings of International Test Conference (ITC), Baltimore (MD), pp. 939–947, October 30 – November 1, 2001, International Test Conference, 2000 L Street, NW, Washington D.C. 20036, 2001.
  46. C. Metra, S. Di Francescantonio, T. M. Mak, B. Riccò, “Evaluation of Clock Distribution Networks’ Most Likely Faults and Produced Effects”, in IEEE Proceedings of The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 357–365, October 24-26, 2001, San Francisco (CA, USA), IEEE Computer Society Press, Los Alamitos (California), 2001.
  47. M. Favalli, C. Metra, “Problems due to open faults in the interconnections of self-checking data-paths”, in IEEE Proceedings of Design, Automation and Test in Europe (DATE) Conference, Paris (France), March 4-8, pp. 612–617, 2002, IEEE Computer Society Press, Los Alamitos (California), 2002.
  48. C. Metra, L. Schiano, M. Favalli, B. Riccò, “Self-Checking Scheme for the On-Line Testing of Power Supply Noise”, in IEEE Proceedings of Design, Automation and Test in Europe (DATE) Conference, Paris (France), pp. 832–836, March 4-8, 2002, IEEE Computer Society Press, Los Alamitos (California), 2002.
  49. D. Rossi, V.E.S. van Dijk, R.P. Kleihorst, A.H. Nieuwland and C. Metra, “Coding Scheme for Low Energy Consumption Fault-Tolerant Bus”, in IEEE Proceedings 8th IEEE International On-Line Testing Workshop, Isle of Bendor (France), pp. 8–12, July 8-10, 2002, IEEE Computer Society Press, Los Alamitos (California), 2002.
  50. L. Schiano, C. Metra and D. Marino, “Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems”, in IEEE Proceedings 8th IEEE International On-Line Testing Workshop, Isle of Bendor (France), pp. 243–247, July 8-10, 2002, IEEE Computer Society Press, Los Alamitos (California), 2002.
  51. D. Rossi, C. Metra and B. Riccò, “Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories”, in IEEE Proceedings IEEE International Workshop on Memory Technology, Design and Testing, Isle of Bendor (France), pp. 27–31, July 10-12, 2002, IEEE Computer Society Press, Los Alamitos (California), 2002.
  52. C. Metra, S. Di Francescantonio, T. M. Mak, “Clock Faults’ Impact on Manufacturing Testing and Their Possible Detection Through On-line Testing”, in IEEE Proceedings of International Test Conference (ITC), Baltimore (MD), October 8-10, 2002, pp. 100-109, International Test Conference, 2025 M Street, N.W., Suite 800, Washington D.C., 20036, 2002.
  53. C. Metra, S. Di Francescantonio, G. Marrale, “On-Line Testing of Transient faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits”, in IEEE Proceedings of The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 6-8, 2002, Vancouver (Canada), pp. 207-215, IEEE Computer Society Press, Los Alamitos (California), 2002.
  54. M. Omaña, D. Rossi and C. Metra, “High Speed and Highly Testable Parallel Two- Rail Code Checker”, in IEEE Proceedings of Design, Automation and Test in Europe (DATE) Conference, Munich (Germany), pp. 608–613, March 4-7, 2003, IEEE Computer Society Press, Los Alamitos (California), 2003.
  55. D. Rossi, V.E.S. van Dijk, R.P. Kleihorst, A.H. Nieuwland and C. Metra, “Power Consumption of Fault Tolerant Codes: the Active Elements”, in IEEE Proceedings 9th IEEE International On-
    Line Testing Symposium”, Kos (Greece), July 7 – 9, 2003, pp. 61-67, IEEE Computer Society Press, Los Alamitos (California), 2003.
  56. L. Di Silvio, D. Rossi and C. Metra, “Crosstalk effect minimization for encoded bus”, in IEEE Proceedings 9th IEEE International On-Line Testing Symposium, Kos (Greece), July 7 – 9, 2003, pp. 214-218, IEEE Computer Society Press, Los Alamitos (California), 2003.
  57. M. Omaña, G. Papasso, D. Rossi and C. Metra, “A Model for Transient Fault Propagation in Combinatorial Logic”, in IEEE Proceedings 9th IEEE International On-Line Testing Symposium, Kos (Greece), July 7 – 9, 2003, pp. 111-115, IEEE Computer Society Press, Los Alamitos (California), 2003.
  58. M. Omaña, D. Rossi, C. Metra, “Novel Transient Fault Hardened Static Latch”, in IEEE Proceedings of International Test Conference (ITC), Baltimore (MD), September 30 – October 2, 2003, pp. 886-892, International Test Conference, 2025 M Street, N.W., Suite 800, Washington D.C., 20036, 2003.
  59. C. Metra, S. Di Francescantonio, M. Omana, “Automatic Modification of Sequential Circuits for Self-Checking Implementation”, in IEEE Proceedings of The International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston (MA), November 2003, pp. 417-424, IEEE Computer Society Press, Los Alamitos (California), 2003.
  60. D. Rossi, S. Cavallotti, C. Metra, “Error Correcting Codes for Crosstalk Effect Minimization”, in IEEE Proceedings of The International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston (MA), November 2003, pp. 257-264, IEEE Computer Society Press, Los Alamitos (California), 2003.
  61. C. Metra, TM Mak, D. Rossi, “Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors”, in IEEE Proceedings of The International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston (MA), November 2003, pp.63-70, IEEE Computer Society Press, Los Alamitos (California), 2003.
  62. C. Metra, TM Mak, M. Omaña, “Are Our Design For Testability Features Fault Secure ?”, in IEEE Proceedings of Design, Automation and Test in Europe (DATE) Conference, Paris (France), pp. 714—715, February 16-20, 2004, IEEE Computer Society Press, Los Alamitos (California), 2004.
  63. J. M. Cazeaux, M. Omaña, and C. Metra, “Low-Area and Fast On-Chip Circuit for Jitter Measurement in Phase-Locked Loop”, in IEEE Proceedings 10th IEEE International On-Line Testing Symposium, Madeira (Portugal), July 12 – 14, 2004, pp. 17-22, IEEE Computer Society Press, Los Alamitos (California), 2004.
  64. J. M. Cazeaux, D. Rossi and C. Metra, “New High Speed CMOS Self-Checking Voter”, in IEEE Proceedings 10th IEEE International On-Line Testing Symposium, Madeira (Portugal), July 12 – 14, 2004, pp. 58-63, IEEE Computer Society Press, Los Alamitos (California), 2004.
  65. C. Metra, TM Mak, M. Omaña, “Fault Secureness Need for Next Generation High Performance Microprocessor Design for Testability Structures”, in Proceedings of 2004 ACM International Conference on Computing Frontiers, Ischia (Italy), pp. 444—450, April 14-16, 2004, ACM ISBN: 1-58113-741-9.
  66. C. Metra, A. Ferrari, M. Omaña and A. Pagni, “Hardware Reconfiguration Scheme for High Availability Systems”, in IEEE Proceedings 10th IEEE International On-Line Testing Symposium, Madeira (Portugal), July 12 – 14, 2004, pp. 161-166, IEEE Computer Society Press, Los Alamitos (California), 2004.
  67. D. Rossi, A. Muccio, A. K. Neiuwland, A. Kotoch and C. Metra, “Impact of ECCs on Simultaneously Switching Outputs Noise for On-Chip Busses of High Reliability Systems”, in IEEE Proceedings 10th IEEE International On-Line Testing Symposium, Madeira (Portugal), July 12 – 14, 2004, pp. 135-140 IEEE Computer Society Press, Los Alamitos (California), 2004.
  68. C. Metra, TM Mak, M. Omaña, “Should We Make Our Design for Testability Schemes Fault Secure ?”, in IEEE Proceedings of The IEEE European Test Symposium, Aiaccio (Corsica), pp. 67—72, May, 2004.
  69. C. Metra, M. Omaña, TM Mak, “Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing”, in IEEE Proceedings of International Test Conference (ITC), Charlotte (NC), pp. 1223 – 1231, October 26- October 28, 2004, International Test Conference, 2025 M Street, N.W., Suite 800, Washington D.C., 20036, 2004.
  70. M. Omaña, D. Rossi, C. Metra, “Fast and Low Cost Deskew Buffer”, in IEEE Proceedings of The International Symposium on Defect and Fault Tolerance in VLSI Systems, Cannes (France), October 11-13, 2004, pp. 202 – 210, IEEE Computer Society Press, Los Alamitos (California), 2004.
  71. M. Omaña, D. Rossi, C. Metra, “Low Cost Scheme for On-Line Clock Skew Compensation”, in IEEE Proceedings of 23rd IEEE VLSI Test Symposium, Palm Springs (California), May 1-5, 2005, pp. 90—95, IEEE Computer Society Press, Los Alamitos (California), 2005.
  72. J. M. Cazeaux, D. Rossi, M. Omaña, C. Metra, and A. Chatterjee, “On Transistor Level Gate Sizing for Increased Robustness to Transient Faults”, in IEEE Proceedings 11th IEEE International On-Line Testing Symposium, Saint Raphael (France), July 6-8, 2005, pp. 23—28, IEEE Computer Society Press, Los Alamitos (California), 2005.
  73. M. Omaña, O. Losco, C. Metra and A. Pagni, “On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits’ Area Overhead and Performance Optimization”, in IEEE Proceedings 11th IEEE International On-Line Testing Symposium, Saint Raphael (France), July 6-8, 2005, pp. 163—168, IEEE Computer Society Press, Los Alamitos (California), 2005.
  74. A. K. Nieuwland, A. Katoch, D. Rossi and C. Metra, “Coding Techniques for Low Switching Noise in Fault Tolerant Busses”, in IEEE Proceedings 11th IEEE International On-Line Testing Symposium, Saint Raphael (France), July 6-8, 2005, pp. 183—189, IEEE Computer Society Press, Los Alamitos (California), 2005.
  75. Y. S. Dhillon, A. U. Diril, A. Chatterjee, and C. Metra, “Output Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits”, in IEEE Proceedings 11th IEEE International On-Line Testing Symposium, Saint Raphael (France), July 6-8, 2005, pp. 35—40, IEEE Computer Society Press, Los Alamitos (California), 2005.
  76. C. Metra, M. Omaña, D. Rossi, JM. Cazeaux, TM Mak, “The Other Side of the Timing Equation: a Result of Clock Faults”, in IEEE Proceedings of The International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterey (California), October 3-5, 2005, pp. 169—177, IEEE Computer Society Press, Los Alamitos (California), 2005.
  77. D. Rossi, M. Omaña, F. Toma, C. Metra,, “Multiple Transient Faults in Logic: an Issue for Next Generation Ics ?”, in IEEE Proceedings of The International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterey (California), October 3-5, 2005, pp. 352—360, IEEE Computer Society Press, Los Alamitos (California), 2005.
  78. D. Rossi, C. Steiner, C. Metra, “Analysis of the Impact of Bus Implemented EDCs on On-Chip SSN”, in IEEE Proceedings of the Design, Automation and Test in Europe (DATE 2006), Munich (Germany), March 6-10, 2006, pp. 59—64, IEEE Computer Society Press, Los Alamitos (California), 2006.
  79. M. Omaña, J. M. Cazeaux, D. Rossi, C. Metra, “Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects”, in IEEE Proceedings of IEEE Design, Automation and Test in Europe (DATE 2006), Munich (Germany) March 6 – 10, 2006, pp. 170—175, IEEE Computer Society Press, Los Alamitos (California), 2006.
  80. C. Metra, D. Rossi, M. Omaña, J.M. Cazeaux, TM Mak, “Can Clock Faults Be Detected Through Functional Test ?”, Proc. of the 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’06), Prague (Czech Republic), April 18 – 21, 2006, pp. 168—173, ISBN: 1-4244-0184-4.
  81. D. Rossi, M. Omaña, C. Metra, A. Pagni, “Checker No-Harm Alarm Robustness”, in IEEE Proceedings of the IEEE International On-Line Testing Symposium, Como (Italy), July 10-12, 2006, pp.275—280, IEEE Computer Society Press, Los Alamitos (California), 2006.
  82. C. Metra, M. Omaña, D. Rossi, J. M. Cazeaux, TM Mak, “Path (Min) Delay Faults and Their Impact on Self-Checking Circuits’ Operation”, in IEEE Proceedings of the IEEE International On-Line Testing Symposium, Como (Italy), July 10-12, 2006, pp.17—22, IEEE Computer Society Press, Los Alamitos (California), 2006.
  83. D. Rossi, J. M. Cazeaux, C. Metra, F. Lombardi, “A Novel Dual-Walled CNT Bus Architecture with Reduced Cross-Coupling Features”, in IEEE Proceedings of the IEEE Conference on Nanotechnology, Cincinnati (Ohio, USA), July 16-20, 2006, IEEE Catalog number 06TH8861C, ISBN 1-4244-0078-3.
  84. X. Ma, J. Huang, C. Metra, F. Lombardi, “Testing Reversible 1D Arrays of Molecular QCA”, in IEEE Proceedings of The International Symposium on Defect and Fault Tolerance in VLSI Systems, Washington DC (USA), October 4—6, 2006, IEEE Computer Society Press, Los Alamitos (California), 2006.
  85. M. Favalli, C. Metra, “Pulse propagation for the detection of small delay defects”, in IEEE Proceedings of the Design, Automation and Test in Europe (DATE 2007), Nice (France), April 16-20, 2007, IEEE Computer Society Press, Los Alamitos (California), 2007.
  86. D. Rossi, P. Angelini, C. Metra, “Configurable Error Control Scheme for NoC Signal Integrity”, in IEEE Proceedings of the IEEE International On-Line Testing Symposium, Crete (Greece), July 9-11, 2007 pp. 1-6, IEEE Computer Society Press, Los Alamitos (California), 2007.
  87. C. Metra, M. Omaña, TM. Mak, S. Tam, “Novel Approach to Clock Fault Testing for High Performance Microprocessors”, in IEEE Proceedings VLSI Test Symposium 2007, May 6-9, Berkeley, CA, 2007, pp. 441—446, IEEE Computer Society Press, Los Alamitos (California), 2007.
  88. X. Ma, J. Huang, C. Metra, F. Lombardi, “Testing Reversible One-Dimensional QCA Arrays for Multiple Faults”, in IEEE Proceedings of The International Symposium on Defect and Fault Tolerance in VLSI Systems 2007, Rome (Italy), September 26-28, 2007, pp. 469-477, IEEE Computer Society Press, Los Alamitos (California), 2007.
  89. C. Metra, M. Omaña, TM. Mak, S. Tam, “Novel Compensation Scheme for Local Clocks of High Performance Microprocessors”, in IEEE Proceedings of the IEEE International Test Conference 2007, Santa Clara (California), October 21-26, 2007, pp. 1-9, International Test Conference, 2025 M Street, N.W., Suite 800, Washington D.C., 20036, 2007.
  90. D. Rossi, P. Angelini, C. Metra, G. Campardo, GP Vanelli, “Risks for Signal Integrity in System in Package and Possible Remedies”, in IEEE Proceedings of the IEEE European Test Symposium 2008, Lake Maggiore (Italy), May 25-29, pp. 165—170, 2008, IEEE Computer Society Press, Los Alamitos (California), 2008.
  91. C. Metra, D. Rossi, M. Omaña, A. Jas, R. Galivanche, “Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach For High Performance Microprocessor Control Logic”, in IEEE Proceedings of the IEEE European Test Symposium 2008, Lake Maggiore (Italy), May 25-29, pp. 171—176, 2008, IEEE Computer Society Press, Los Alamitos (California), 2008.
  92. C. Metra, M. Omaña, TM Mak, A. Rahman, S. Tam, “Novel On-Chip Clock Jitter Measurement Scheme For High Performance Microprocessors”, IEEE Proceedings of the 23th IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’08), Cambridge (MA), October 1-3, pp. 465-473, 2008, IEEE Computer Society Press, Los Alamitos (California), 2008.
  93. X. Ma, J. Huang, F. Chiminazzo, D. Rossi, C. Metra, F. Lombardi, “Resistive Crossbar Switching Networks to Implement Inherently Fault Tolerant Nano LUTs”, IEEE Proceedings of the 1st IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems (NDCS’08), Cambridge (MA), September 29-30, 2008, pp. 21 – 24, 2008,, IEEE Computer Society Press, Los Alamitos (California), 2008.
  94. C. Metra, D. Rossi, M. Omaña, A. Jas, R. Galivanche, “Low Cost On-Line Testing of the Scheduler of High Performance Microprocessors”, Proceedings of the IEEE European Test Symposium 2009, Sevilla (Spain), May 25-29, 2009.
  95. C. Metra, “Trading Off Dependability and Cost for Nanoscale High Performance Microprocessors: The Clock Distribution Problem”, Proceedings of the IEEE Workshop on Dependable and Secure Nanocomputing 2009 (WDSN09), Estoril (Portugal), June 29, 2009, pp. D4-D5, 2009, IEEE Catalog Number: CFP09048-CDR, ISBN: 978-1-4244-4421-2, Library of Congress: 2009902897
  96. (Best Paper Award) M. Omaña, D. Rossi, C. Metra, “Novel High Speed Robust Latch”, IEEE Proceedings of the 23th IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), Chicago (IL), October 7-9, pp. 65-73, 2009, IEEE Computer Society Press, Los Alamitos (California), 2009.
  97. M. Omaña, M. Marzencki, R. Specchia, C. Metra, B. Kaminska, “Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors”, IEEE Proceedings of the 23th IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), Chicago (IL), October 7-9, pp.127-135, 2009, IEEE Computer Society Press, Los Alamitos (California), 2009.
  98. M. Omaña, D. Rossi, N. Bosio, C. Metra, “Novel Low-Cost Aging Sensor”, in ACM Proceedings of the International Conference on Computing Frontiers, Bertinoro (Italy), May 17-19, 2010.
  99. D. Rossi, M. Omaña, G Berghella, C. Metra, A. Jas, T. Chandra, R. Galivanche, “Low Cost and Low Intrusive Approach to Test On-Line the Scheduler of High Performance Microprocessors”, in ACM Proceedings of the International Conference on Computing Frontiers, Bertinoro (Italy), May 17-19, 2010.
  100. M. Omaña, D. Rossi, N. Bosio, C. Metra, “Self-Checking Monitor for NBTI Due Degradation”, in Proc. of IEEE International Mixed-Signals, Sensors, and Systems Test Workshop, June 7-9, 2010, Montpellier, France, 2010.
  101. D. Rossi, M. Omaña, D. Giaffreda, C. Metra, “Secure Communication Protocol for Wireless Sensor Networks”, in IEEE Proc. of the 8th IEEE East-West Design & Test Symposium (EWDTS), September 17-20, 2010, IEEE Computer Society Press, Los Alamitos (California), 2010.
  102. M. Omaña, D. Giaffreda, C. Metra, TM Mak, S. Tam, A. Rahman, “On-Die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter”, IEEE Proceedings of the 24th IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), Kyoto (Japan), October 6-8, 2010, IEEE Computer Society Press, Los Alamitos (California), 2010.
  103. D. Rossi, M. Omaña, C. Metra, “Transient Fault and Soft Error on-Die Monitor”, IEEE Proceedings of the 24th IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), Kyoto (Japan), October 6-8, 2010, IEEE Computer Society Press, Los Alamitos (California), 2010.
  104. D. Rossi, N. Timoncini, M. Spica, C. Metra, “Error Correcting Code Analysis for Memory High Reliability and Performance”, in IEEE Proc. of the Design, Automation and Test in Europe (DATE 2011), Grenoble (France), March 14-18, 2011, IEEE Computer Society Press, Los Alamitos (California), 2011.
  105. D. Rossi, M. Omaña, C. Metra, A. Paccagnella, “Impact of Aging Phenomena on Soft Error Susceptibility”, IEEE Proceedings of the IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’11), Vancouver (Canada), October 3-5, 2011, pp.18-24, IEEE Computer Society Press, Los Alamitos (California), 2011.
  106. D. Giaffreda, M. Omaña, D. Rossi, C. Metra, “Model for Thermal Behavior of Shaded Photovoltaic Cells Under Hot-Spot Condition”, IEEE Proceedings of the IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’11), Vancouver (Canada), October 3-5, 2011, pp. 252-258, IEEE Computer Society Press, Los Alamitos (California), 2011.
  107. M. Omaña, D. Rossi, G. Collepalumbo, C. Metra, F. Lombardi, “Faults Affecting the Control Blocks of PV Arrays and Techniques for Their Concurrent Detection”, in IEEE Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’12), Austin (Texas, USA), October 3-5, 2012, pp. 199-204, IEEE Computer Society Press, Los Alamitos (California), 2012.
  108. R. Vimalathithan, D. Rossi, M. Omaña, C. Metra, M. L. Valarmathi, “Polynomial Based Key Distribution Scheme for WPAN”, in Proceedings of 3rd International Conference on Cryptology and Computer Security 2012, June 4-6 2012, Langkawi, Malaysia, 2012.
  109. C. Bolchini, A. Miele, C. Sandionigi, M. Ottavi, S. Pontarelli, A. Salsano, C. Metra, M. Omaña, D. Rossi, M. Sonza Reorda, L. Sterpone, M. Violante, S. Gerardin, M. Bagatin, A. Paccagnella, “High-reliability Fault Tolerant Digital Systems in Nanometric Technologies: Characterization and Design Methodologies” in IEEE Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’12), Austin (Texas, USA), October 3-5, 2012, pp. 121-125, IEEE Computer Society Press, Los Alamitos (California), 2012.
  110. M. Omaña, F. Fuzzi, D. Rossi, C. Metra, C. Tirumurti, R. Galivanche, “Novel Approach to Reduce Power Droop During Scan-Based Logic BIST”, in IEEE Proceedings of the IEEE European Test Symposium 2013, Avignon (France), May 27-31, 2013, IEEE Computer Society Press, Los Alamitos (California), 2013.
  111. M. Omaña, D. Rossi, E. Beniamino, C. Metra, C. Tirumurti, and R. Galivanche, “Power Droop Reduction During Launch-On-Shift Scan-Based Logic BIST” in IEEE Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Amsterdam, October 1-3, 2014, pp. 21-26, IEEE Computer Society Press, Los Alamitos (California), 2014.
  112. M. Omaña, L. A. Adanaque, C. Metra, D. Rossi, “On Aging of Latches’ Robustness”, in Proc. of Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN) Workshop, 2015.
  113. M. A. Koche, A. Dalirsni, A. Bernabei, M. Omaña, C. Metra, H.-J. Wunderlich, “Intermittent and Trnsient Fault Diagnosis on Sparse Code Signatures”, in IEEE Proc. of Int’l. Asian Test Sympsium, Mumbay (India), 22-25 November, 2015
  114. M. Omaña, A. Fiore, C. Metra, “Inverters’ Self-Checking Monitors for Reliable Photovoltaic Systems”, in IEEE Proceedings of IEEE Design, Automation and Test in Europe (DATE 2016), Dresden (Germany), 14 – 18 March, 2016
  115. C. Metra, “Test and Reliability Challenges for High Performance, Nanotechnology Circuits and Systems", in IEEE Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Košice (Slovakia), April 20-22, 2016, pp. 1-2

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